Studying the Temperature Field in a Power Integrated Circuit and Optimizing the Topology of Its Electrical Connections for Improving Its Miniaturization Parameters

Abstract

The thermal fields and distributed parasitic elements in the power integrated circuit (PIC) structure are investigated. The 3D temperature field of the PIC is calculated assuming that its heat-generating elements (silicon crystals) are located on the ceramic plate surface at the nodes of square lattice with a specified size. During the modeling, different geometric parameters of the crystals, metallization layers, and lattice spacing of the simulated thermal field were used. The temperature distribution in the module structure along the vertical axis passing through the semiconductor crystal center was calculated, and it has been found from the calculation results that the main temperature difference between the crystal and medium falls across the ceramic plate layer and the heat-conducting paste layer between the module base and cooler. The temperature distribution over the crystal surface was analyzed, and it has been confirmed from the analysis results that the temperature in the crystal peripheral regions is essentially lower than it is at the crystal center. The area of these relatively cold regions is about half the crystal total area. It has been concluded that in designing a module, its elementary cell’s maximal period can be limited at a level corresponding to twice the crystal linear size. The obtained calculation results made it possible to determine the optimal positions of placing the semiconductor crystals on the power module’s ceramic plate surface and the topology of their electrical connections. It has been found that the optimal positioning of crystals according to the minimum temperature overheating criterion does not correspond to the optimal positioning in terms of minimizing parasitic structural elements. For this reason, weight coefficients taking into account the dominant influence of different factors were adopted. It has been demonstrated that with increasing the switched power level, it becomes advisable to place semiconductor crystals on separate ceramic plates.